Hardware and virtual machines
Cambridge AS & A Level Computer Science 9618 · Paper 3 · Unit 15
Paper 3 · Unit 15. RISC/CISC, pipelining, parallel processing, virtual machines, Boolean algebra and circuits.
1. RISC and CISC processors
| RISC | CISC |
|---|---|
| Small set of simple instructions | Large set of complex instructions |
| Each instruction takes about one clock cycle | Instructions take several cycles |
| Fixed-length instructions; easier to pipeline | Variable-length instructions; harder to pipeline |
| More general-purpose registers | Fewer registers; more memory access |
| Compiler does more work; programs are longer | Hardware does more work; shorter programs |
Pipelining overlaps the stages of several instructions (fetch, decode, execute, memory access, write back) so one instruction can complete each cycle. When an interrupt occurs, the pipeline can be flushed, or the instructions already in it completed, before the ISR is run.
2. Parallel processing
| Architecture | Meaning |
|---|---|
| SISD | Single instruction, single data: one processor (traditional) |
| SIMD | Single instruction, multiple data: same operation on many items, e.g. graphics, sound |
| MISD | Multiple instruction, single data: rare |
| MIMD | Multiple instruction, multiple data: multicore processors running different tasks |
Massively parallel computers link huge numbers of processors to work on one problem; programs must be written to split the work.
3. Virtual machines
A virtual machine is software that emulates a computer, so a guest operating system or program runs on a host system. Benefits: run several OSs on one computer, test software safely, run old software. Drawbacks: slower than real hardware and needs extra memory and processing.
4. Boolean algebra and Karnaugh maps
Key laws: De Morgan’s NOT(A AND B) = NOT A OR NOT B, and NOT(A OR B) = NOT A AND NOT B. Also identity, absorption, distribution and double complement laws.
A Karnaugh map simplifies an expression: place the 1s from the truth table (Gray code order 00, 01, 11, 10), group adjacent 1s in rectangles of 1, 2, 4 or 8 (as large as possible, wrapping round the edges), then write one term per group keeping only the variables that do not change.
5. Adders and flip-flops
A half adder adds two bits: Sum = A XOR B, Carry = A AND B. A full adder adds two bits plus a carry in, using two half adders and an OR gate.
Try it: full adder
Click the inputs to toggle them.
A flip-flop stores one bit and is the basis of registers and SRAM. An SR flip-flop has Set and Reset inputs; S = R = 1 is invalid. A JK flip-flop adds a clock and removes the invalid state: J = K = 1 toggles the output.
6. Examiner tips
- RISC vs CISC: compare in matched pairs.
- Pipelining: draw a table of stages against clock cycles if asked.
- Karnaugh maps: use Gray code order and the largest possible groups.
- JK flip-flop is used because it has no invalid state.
- Show each Boolean law you use when simplifying.
7. Practice questions
Practice: answer and check instantly
Type a short answer, then press Check or Enter.
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RISC.
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SIMD.
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MIMD.
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XOR.
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AND.
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JK flip-flop.
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De Morgan’s law.
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Gray code.
Exam-style questions
9. Explain how pipelining improves processor performance. [3]
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The fetch, decode and execute stages of different instructions overlap [1] · while one instruction executes, the next is decoded and another fetched [1] · so ideally one instruction completes every clock cycle, increasing throughput [1].
10. Give two benefits and one drawback of virtual machines. [3]
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Can run several operating systems on one machine [1] · safe testing/isolation, or run legacy software [1] · drawback: slower performance / needs more resources than real hardware [1].
8. Topic test: predict your grade
Topic test: predict your grade
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Frequently asked questions
What is the difference between RISC and CISC?
RISC processors use a small set of simple, fixed-length instructions that take about one clock cycle each. CISC processors use many complex instructions that take several cycles.
How do you simplify a Karnaugh map?
Place the 1s from the truth table in Gray code order, group adjacent 1s in the largest possible rectangles of 1, 2, 4 or 8, then write one term per group using only the variables that do not change.
What is the difference between an SR and a JK flip-flop?
An SR flip-flop has an invalid state when both inputs are 1. A JK flip-flop is clocked and toggles its output when both J and K are 1, so it has no invalid state.