Processor fundamentals

Paper 1 · Unit 4. CPU architecture, the fetch-execute cycle, assembly language and bit manipulation.

1. Von Neumann architecture

In the Von Neumann model, a single processor executes instructions one at a time, and programs and data are stored together in the same main memory (the stored program concept). Instructions are fetched from memory, decoded and executed in sequence.

2. Registers

Registers are very fast storage locations inside the CPU. General-purpose registers hold data temporarily; special-purpose registers have fixed roles.

Register	Role
PC (Program Counter)	Holds the address of the next instruction
MAR (Memory Address Register)	Holds the address being read from or written to
MDR (Memory Data Register)	Holds the data or instruction just read, or about to be written
CIR (Current Instruction Register)	Holds the instruction being decoded and executed
ACC (Accumulator)	Holds the result of calculations
IX (Index Register)	Holds a value added to an address in indexed addressing
Status Register	Holds flags, e.g. carry, overflow, negative, zero, interrupt

3. CPU components and buses

Component	Role
ALU	Carries out arithmetic and logic operations
Control Unit (CU)	Decodes instructions and sends control signals to coordinate the processor
System clock	Generates timing signals that synchronise operations
Immediate Access Store (IAS)	Memory the CPU can access directly (RAM)

Bus	Direction	Carries
Address bus	One-way: CPU to memory	The address of the memory location
Data bus	Two-way	Data and instructions
Control bus	Two-way	Control signals, e.g. read, write, clock, interrupt

4. Factors affecting performance

Factor	Effect
Processor type and number of cores	More cores can run more instructions in parallel, if the software supports it
Bus width	A wider data bus moves more bits at once; a wider address bus can address more memory
Clock speed	More cycles per second means more instructions per second (but more heat)
Cache memory	Larger cache means frequently used data is found faster, without going to RAM

5. Ports

Peripherals connect through ports. USB is a universal serial port for many devices and also supplies power. HDMI carries high-definition digital video and audio. VGA is an older analogue video port.

6. The fetch-execute cycle

In register transfer notation, [x] means “the contents of x”:

MAR ← [PC]
PC ← [PC] + 1 ; MDR ←



undefined



CIR ← [MDR]
(decode, then execute)

The PC is incremented during the fetch so it always points to the next instruction. Jumps change the PC directly.

7. Interrupts

An interrupt is a signal from hardware or software that needs the processor's attention, e.g. a printer out of paper, a key press, a timer, or a division by zero.

1. At the end of each fetch-execute cycle, the processor checks for interrupts.
2. If there is one with higher priority than the current task, the current register contents are saved (on the stack).
3. The Interrupt Service Routine (ISR) for that interrupt is loaded and run.
4. The saved registers are restored and the original task continues.

8. Assembly language

Assembly language uses mnemonics (e.g. LDD, ADD, STO) that map one-to-one onto machine code. An assembler translates it. A two-pass assembler first builds a symbol table of labels and their addresses, then on the second pass replaces labels and mnemonics with machine code.

Mode	Operand means	Example
Immediate	The value itself	LDM #5 loads 5
Direct	The address of the value	LDD 200 loads the contents of 200
Indirect	The address holding the address of the value	LDI 200
Indexed	The address plus the IX contents	LDX 200 loads from 200 + [IX]
Relative	An offset from the current address	JMP +3

Instruction groups: data movement (LDM, LDD, LDI, LDX, LDR, MOV, STO), input/output (IN, OUT), arithmetic (ADD, SUB, INC, DEC), comparisons and jumps (CMP, CMI, JPE, JPN, JMP), and END.

9. Bit manipulation

Logical shift: bits move left or right and 0s fill the gap. Shifting left once multiplies an unsigned value by 2; shifting right divides by 2. Arithmetic shift right keeps the sign bit. Cyclic shift moves bits off one end and back in at the other.

Masks test or change specific bits: AND with a mask clears bits (keep bits where the mask is 1), OR sets bits, and XOR toggles bits. This is used to test flags or monitor device status.

10. Examiner tips

1. Use register names correctly: MAR holds an address, MDR holds data.
2. The PC is incremented in the fetch stage, before execution.
3. Address bus is one-way; data and control buses are two-way.
4. Interrupts are checked at the end of each cycle, and registers are saved before the ISR runs.
5. In assembly traces, keep track of the ACC after every instruction.
6. Immediate vs direct: # means the number itself.

11. Practice questions

12. Topic test: predict your grade